The present invention relates to the manufacturing, testing, and packaging of integrated circuits. Specific embodiments of the invention relate to an integrated circuit structure that includes an interconnect pad having first and second separate regions for bonding and probing the pad, respectively, and a method for forming and testing such a structure. The apparatus and methods of the present invention are also of use with other devices that are probe tested and have wire-bonding connections such as semiconductor packaging (e.g., flipchip, BGA, and multi-chip modules) and other printed or ceramic circuit boards. The apparatus and method of the present invention are of use with a variety of interconnection pad material, such as, gold, aluminum, copper, gold plated aluminum, and the like.
Integrated circuit performance and reliability are typically evaluated at the wafer level prior to packaging. Wafer level testing typically includes mechanically probing interconnect pads on the wafer to electrically test the wafer""s electronic structures. Interconnect pads provide the electrical connection between the wafers electronic structures and the outside world. Probing interconnect pads causes galling of the pads that may cause the pad to fail during a wire bonding process, during a stress test of a wire bond or during normal use of an integrated circuit device, or may simply weaken the interconnect pads.
Traditionally, interconnect pads were probed no more than one or two times as additional probing often left interconnect pads galled to such an extent that wire bonding to the pads was impractical. As integrated circuits have become more complex, however, it is sometimes desirable to probe interconnect pads multiple times to perform a variety of functions and/or tests on the integrated circuit. For example, memory devices, such as flash memory, may be initially probed for general functionality testing and to program the memory cells. The memory device may be probed a second, third, or mores times subsequent to being baked to determine the quality of the memory cells. Other integrated circuit devices may have pads that are probed as many as seven, eight, or more times prior to wire bonding. Each probing of an interconnect pad increases the chance the pad will fail during wire bonding or subsequent.
One aspect of increasing integrated circuit complexity is the circuits continue to become smaller. Smaller integrated circuits have driven a desire for interconnect pads that are relatively smaller, have finer pitch, and have smaller spacing between the pad edges. Relatively smaller interconnect pads have smaller surface area to adhere to underlying integrated circuit structures increasing the chance pads will be lifted during a wire bonding process or during normal use of the device. Moreover, as the size of interconnect pads has been driven down so too has the size of probes used to probe the pads. Probes of relatively smaller size have relatively sharper tips and tend to increase pad galling during probing. Accordingly, relatively smaller interconnects pads are further limited in the number of times the pads may be probed prior to being galled to such an extent that wire bonding is not practical.
Increased complexity of integrated circuit devices has not only driven down interconnect pad size and pitch, increased complexity has also driven an increase in the number of interconnect pads on a given device. Earlier generations of integrated circuit devices typically had a few to several tens of interconnects pads per device. Today""s increasingly complex integrated circuit devices may have hundreds if not thousands of interconnect pads. As the number of interconnect pads increases so to does the number of probes required to probe a device. Keeping hundreds, and possibly thousands, of probes on a probing device optimally coplanar is relatively costly. As a probing device is repeatedly used the probes deviate from optimum coplanarity and thus require greater overdriving forces to ensure all probes mechanically contact their designate interconnect pads. Increased overdriving causes the probes to gall the interconnect pads more severely than lower driving forces used for more optimally coplanar probes.
Solutions have been sought to support interconnect pads from underneath to limits the deleterious effects of probing on structures underlying a pad. For example, solutions have been sought to place shock-absorbing structures below a pad to prevent such damage. However, while shock-absorbing structures under interconnect pads may protect structures underlying the pad, the pad itself remains vulnerable to probe damage that may lead to subsequent lifting of the pad during wire bonding or normal use of an integrated circuit device.
Accordingly, the semiconductor industry continues to develop new interconnect pads that suffer less from the deleterious effect caused by multiple probing, decreased pad size, wire bonding, and general device use.
The present invention provides a solution to the problem of lifting bond wires and lifting interface pads in integrated circuit devices due in part to test probes galling and weakening the interconnect pads during functional and reliability test probing. In doing so, the invention enables a lowering of the chance a bond wire will be lifted in normal operation of an integrated circuit and enables a lowering of the chance an interconnect pad will be lifted during a wire bond process or in the normal operation of an integrated circuit.
According to one embodiment of an apparatus of the present invention, an integrated circuit has an interconnect region that includes an interconnect pad having a first portion and a second portion. A dielectric passivation layer overlies portions of the integrated circuit device and has first and second opening corresponding to and exposing the first and second portions of the interconnect pad. A portion of the passivation layer overlies a portion of the interconnect pad between the first portion and the second portion of the pad.
In another embodiment of the invention, an integrated circuit has an interconnect region that includes an interconnect pad having a first portion and a second portion and a visible indicator indicates the division between the first portion and the second portion of the interconnect pad.
According to one embodiment of a method of the present invention, an interconnect pad is formed on an integrated circuit device wherein the interconnect pad has first and second portion and the second portion is probed by a probing device and a bond wire is bonded to the first portion of the interconnect pad.
These and other embodiments of the present invention, as well as its advantages and features, are discussed in more detail in conjunction with the text below and attached figures.